In a recent interaction with Industry Outlook, Navin Bishnoi, Country Head & AVP of HW Engineering (Compute and Custom Solutions), Marvell India shares insights on the current status of semiconductor manufacturing in India, particularly focusing on the recent breakthroughs and advancements in the industry and more. Navin Bishnoi is an industry leader, who oversees custom silicon hardware engineering and serves as the Country Head for Marvell Semiconductor operations in India. With close to three decades of experience acquired from various roles in multinational companies, he spearheads Marvell India to new heights.
Could you share some insights into the current status of semiconductor manufacturing in India, particularly focusing on recent breakthroughs and advancements in the sector?
Today, there is a significant emphasis on semiconductors globally and in India as well. India has a well-established design ecosystem in the semiconductor industry, with over four decades of presence. Many design firms, both international and domestic, have been involved in creating designs for various sectors including automotive, data centers, IoT, sensors, and carrier networking.
Many of those designs goes through global footprints (supply chain) of manufacturing and productization, and there has been a continuous ask to evolve the local ecosystem - extending to the manufacturing, assembly, packaging, and testing phase. Some of the key factors that drive these aspirations (or ask) include geopolitical considerations and the desire for self-sufficiency. Other factors to consider are the level of imports happening and the potential for domestic manufacturing, consumption, and subsequent exporting. These aspects are shaping policies, ecosystem development, and ultimately the establishment of manufacturing entities (eco-system).
Currently, the focus in this sector is evolving from fabless design houses to a complete supply chain including IP, EDA, Design, manufacturing, OSAT, as well as semiconductor R&D. The manufacturing process begins with Wafer Fabrication (after design is complete). It starts with wafer preparation, where silicon wafers are cleaned and polished. Then, various processes like etching, deposition, photolithography, ion implantation, annealing, and chemical mechanical planarization (CMP) are used to create the intricate patterns on the wafer surface. The next step after fabrication is Packaging and Testing, where the individual chips are cut from the wafer and packaged. Packaging involves encapsulating the chip in protective material and connecting it to external pins. Testing ensures that each chip functions correctly. Faulty chips are discarded, while functional ones proceed to the next stage. Finally, the chips are taken through Assembly and Integration, into larger systems or devices. This could involve mounting them on printed circuit boards (PCBs), connecting them to other components, and assembling the final product. The entire lifecycle aims for efficiency, quality, and reliability.
There is a significant amount of activity occurring in the manufacturing industry with global/MNC players, local EMS houses, and new ventures entering the semiconductor manufacturing ecosystem. This is validated by the announcement of a new fab, expansions of the existing fab (SCL) to be a Semiconductor R&D facility with newer technology nodes, and the growth in EMS and assembly houses. There are several opportunities in manufacturing which will support the surge in consumption within the country with the widespread digitalization and automation we are witnessing throughout the country whether it is within buildings, campuses, smart cities, or the governance.
This incorporates numerous data center, cloud, as well as connectivity technologies combined with an increasing focus on automotive mobility, EVs & telecommunications. Several different cases & industries in the country are contributing to the demand for this manufacturing and hence accelerating the semiconductor ecosystem development.
The integration of connectivity and networking technologies profoundly influences semiconductor manufacturing; how does this integration specifically impact the advancement of AI applications within this industry?
The Artificial Intelligence applications are interesting. What we have witnessed is likely one of the practical uses or scenarios which are frequently discussed with regard to ChatGPT, which involves significant usage of prompt engineering. This is a creative way of generating new content, results, or images. However, this is just the beginning. The AI applications will be leveraged by several sectors which include FMCGs, e-commerce, retail, real estate, animation, art, the food industry, and more.
When people think about AI today, the conversation often centers around GPUs, but that is changing. Customized silicon which can be optimized for particular AI models or infrastructure is rising in popularity because it can deliver more performance per watt than standardized GPUs. With data centers requiring tens of megawatts or more of power capacity, power consumption at the chip level is a pressing concern.
Along with that, we are seeing more attention paid to networking and optical interconnects. Training AI models can sometimes require tens of thousands of AI accelerators spread across a large data center or sometimes multiple sites. The data does not flow in a single direction, from servers to switch fabrics and then out to the network, it needs all the components to be connected. As a result, the connections far outnumber the accelerators. Today, there are roughly two optical connections for every accelerator. As the numbers increase, the number of layers of switching will increase. This ratio may go from 4 to one or even higher. Developing efficient network architectures that also consume minimal power is imperative.
With the rapid proliferation of AI technologies across various industries, how do companies anticipate addressing the growing demand for highly interconnected and networked semiconductor solutions?
Most companies should focus on two key factors: speed and power. Inside data centers, the optical connections between racks are moving from 800 Gbps to 1.6T Tbps and it will double again in two to three years. The connections between data centers, which can extend for hundreds of kilometers, are moving up to 800 Gbps. The speeds are needed to keep up with the growing volume of data traffic, which continues to double every two to three years. Power consumption per bit on these optical links is declining by around 30% per generation. Total power consumption, however, has been rising. Some have said that the power consumed by connectivity could rise from its traditional 5 percent level to 12% or more without further innovation. One of the big challenges for AI networking will revolve around commercializing technologies such as silicon photonics, a method of making optical components in silicon, to keep power and cost down.
We’re also going to see changes at the server level. Chips inside servers are still connected by copper. While optical will take over more of these tasks in the long term. We will see innovations in copper in the near term. Chips called retimers which effectively can turbocharge signals will increasingly be used, for instance.
Networking is the nervous system of computing. It has to perform at a high level to keep up with the growing size and complexity of AI workloads. The gains in performance, however, have to be achieved efficiently. Networking might be only a portion of total power consumption, but it’s one that needs to be rigorously monitored.
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