Samsung Foundry is poised to unveil its third generation process technology, SF2, featuring gate-all-around (GAA) transistors at the VLSI Symposium 2024 in June. This marks the company's entry into the 2nm-class fabrication process, promising notable enhancements in performance and efficiency.
On June 19, 2024, Samsung will provide comprehensive insights into its SF2 fabrication technology. Leveraging a refined multi-bridge channel field-effect transistor architecture and a distinctive epitaxial and integration process, SF2 is anticipated to elevate transistor performance by 11–46 percent and reduce variability by 26% compared to an unspecified FinFET-based process. Moreover, leakage is projected to decrease by approximately 50%.
According to Samsung, SF2 maximizes the benefits of gate-all-around technology by addressing scaling challenges and GAA structure conflicts. The technology boosts the performance of both narrow and wide NS transistors, with gains ranging from 11% to 46%. Additionally, it achieves a 26% reduction in transistor global variation compared to FinFET, resulting in a significant 50% reduction in leakage distribution.
Samsung is not only pushing technological boundaries but also fortifying its ecosystem for the 2nm-class fabrication process. Collaborating with over 50 intellectual property (IP) partners and holding more than 4,000 IP titles, Samsung is working towards optimizing Cortex-X and Cortex-A cores with its gate-all-around transistor-based manufacturing technologies through a partnership with Arm.
The design infrastructure development for Samsung's SF2 process technology is slated for completion in Q2 2024, allowing chip development partners to commence product design for the production node.
